C-CREST Technique for Combinational Logic SET Testing

Author

Ahlbin, J.R. ; Black, J.D. ; Massengill, L.W. ; Amusan, O.A. ; Balasubramanian, A. ; Casey, M.C. ; Black, D.A. ; McCurdy, M.W. ; Reed, R.A. ; Bhuva, B.L.

Author_Institution

Vanderbilt Univ., Nashville, TN

Volume

55

Issue

6

fYear

2008

Firstpage

3347

Lastpage

3351

Abstract

SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM´s 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty.

Keywords

CMOS digital integrated circuits; combinational circuits; flip-flops; 9SF CMOS process; C-CREST technique; combinational circuit for radiation effects self-test; combinational logic SET testing; latch errors; minimum speed penalty; size 90 nm; underwent broadbeam testing; Built-in self-test; CMOS logic circuits; CMOS process; Circuit testing; Combinational circuits; Logic design; Logic testing; Propagation delay; Radiation effects; Single event transient; Combinational logic; DICE latch; single event; single event transient; single event upset; window of vulnerability;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2008.2005900

Filename

4723753