• DocumentCode
    1048183
  • Title

    Evaluation of multilevel memories

  • Author

    Mattson, Richard L.

  • Author_Institution
    IBM Research Laboratory, San Jose, California
  • Volume
    7
  • Issue
    4
  • fYear
    1971
  • fDate
    12/1/1971 12:00:00 AM
  • Firstpage
    814
  • Lastpage
    819
  • Abstract
    Proposed memory hierarchy technologies and configurations are usually evaluated by repeated running of "typical" jobs through simulated hierarchies while various parameters are adjusted. Simulation is too slow to be a tool for selecting among the choices in 1) technologies to be included, 2) implementation of each technology, and 3) management of data flow in the hierarchy. Four current hardware-managed hierarchies are described in a manner which parameterizes their design. The evaluation process is described in terms of address traces, hit ratios, and system cost performance. Stack processing is then described as a replacement for simulation that obtains hit-ratio data 1000 times faster than before. Finally, an example is given to illustrate how to select between two competing technologies, how to design the best hierarchy, and how to determine the information flow which optimizes the total cost performance of the system.
  • Keywords
    Memory hierarchies; Automatic control; Computational modeling; Conference management; Cost function; Design optimization; Hardware; Knowledge management; Memory management; Operating systems; Technology management;
  • fLanguage
    English
  • Journal_Title
    Magnetics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9464
  • Type

    jour

  • DOI
    10.1109/TMAG.1971.1067237
  • Filename
    1067237