Effect of silicon-gate resistance on the frequency response of MOS transistors

A polycrystalline silicon gate has finite sheet resistivity, typically in the range of tens of ohms per square. The resulting gate resistance and the gate capacitance form a distributed RC network. The gate voltages appearing along this distributed network, hence, the summation drain current, is delayed from the input voltage applied to the contact pad(s). The delay of the distributed RC network is analyzed for both small and large signals. The analysis shows that when the RC time constant of the gate is comparable to the period of the signal, the frequency response is degraded. This time constant varies as the square of the gate width. For a gate width in the fractional millimeter range (typical of output MOS transistors in an integrated circuit), the time constant may be in the 100-ns range; for gate width in the 10-µ range, in the subnanosecond range.