• DocumentCode
    1050989
  • Title

    Evolvable hardware for lossless compression of very high resolution bi-level images

  • Author

    Sakanashi, H. ; Iwata, M. ; Higuchi, T.

  • Author_Institution
    Adv. Semicond. Res. Center, Nat. Inst. of Adv. Ind. Sci. & Technol., Ibaraki, Japan
  • Volume
    151
  • Issue
    4
  • fYear
    2004
  • fDate
    7/18/2004 12:00:00 AM
  • Firstpage
    277
  • Lastpage
    286
  • Abstract
    A compression method for image data with very high resolution, and an evolvable hardware chip implementing the process quickly are proposed. The current international standard for bi-level image coding, JBIG2, is modified by the proposed method to achieve high compression ratios, where compression parameters are optimised by search methods (primarily a genetic algorithm that has been extended and specialised for this problem). The results of computer simulations show a 23% improvement in compression ratios with the proposed method compared to JBIG2, and demonstrate that the optimisation process can be completed very quickly, even with software execution. The experiment shows that when the method is implemented by hardware with an evolvable hardware chip, the processing is dramatically faster than execution with software. Activities concerning ISO standardisation to adopt part of the technology used in this method to the JBIG2 standard are also described.
  • Keywords
    collision avoidance; controllers; evolutionary computation; field programmable gate arrays; mobile robots; FPGA-based controller; Khepera robot; actuator; complex system design; custom-off-the-shelf hardware; evolutionary algorithm; evolvable hardware; fitness-dependent mutation rate; mobile robot; robot controller; sensor data; sensor faults;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:20040015
  • Filename
    1318862