DocumentCode
1052129
Title
A byte organized NMOS/CCD memory with dynamic refresh logic
Author
Varshney, Ramesh C. ; Guidry, Mark R. ; Amelio, Gilbert F. ; Early, James M.
Author_Institution
Fairchild Research and Development, Palo Alto, CA
Volume
23
Issue
2
fYear
1976
fDate
2/1/1976 12:00:00 AM
Firstpage
86
Lastpage
92
Abstract
A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are descried. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.
Keywords
Charge coupled devices; Circuits; Clocks; Logic devices; Logic functions; MOS devices; Random access memory; Shift registers; Silicon; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1976.18357
Filename
1478371
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