DocumentCode
1053112
Title
An efficient flexible buffered memory system
Author
Pohm, Arthur V. ; Agrawal, Om P. ; Cheng, Cheng-wen ; Shimp, Alton C.
Author_Institution
Iowa State University, Ames, Iowa.
Volume
9
Issue
3
fYear
1973
fDate
9/1/1973 12:00:00 AM
Firstpage
173
Lastpage
179
Abstract
A flexible low cost multiclass memory system has been evaluated and constructed to accommodate memory sizes from 128 000 to 4 000 000 ten-bit bytes. For 1.2 to 1.5 μs cycle time memory modules, typical system cycle times range from 0.25 to 0.40 μs. Provision is made for conveniently varying the block size, the number of blocks per class, and the number of classes. An efficient directory and update list are achieved in the multiclass system by a high-speed segmented memory using memory cells with half the access time of the buffer memory. The directory and update list for any class are accessed by simultaneously reading all segments. Comparison and list manipulation circuitry is shared by all classes. A cost evaluation shows that at the present state of technology, the buffer increases the cost of a 500 000 byte memory by about 8% while decreasing the effective cycle time by a factor of three.
Keywords
Buffered memories; Memories; Australia; Costs; Magnetic domain walls; Packaging; Performance evaluation; Physics; Solid state circuits; System performance;
fLanguage
English
Journal_Title
Magnetics, IEEE Transactions on
Publisher
ieee
ISSN
0018-9464
Type
jour
DOI
10.1109/TMAG.1973.1067669
Filename
1067669
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