DocumentCode
105438
Title
Copula Models of Correlation: A DRAM Case Study
Author
Shirley, C. Glenn ; Daasch, W. Robert
Author_Institution
Integrated Circuits Design & Test Lab., Portland State Univ., Portland, OR, USA
Volume
63
Issue
10
fYear
2014
fDate
Oct. 2014
Firstpage
2389
Lastpage
2401
Abstract
Variable bit retention time observed in a 65-nm dynamic random access memory (DRAM) case study will cause miscorrelation between retention times occurring in Test and Use. Conventional multivariate normal statistics cannot adequately model this miscorrelation. A more general copula-based modeling approach, widely used in financial and actuarial modeling, solves this problem. The DRAM case study shows by example how to use copula models in test applications. The method includes acquiring data using a test vehicle, fitting the data to a copula-based statistical model, and then using the model to compute producer- and customer-oriented figures of merit of a product, different from the test vehicle. Different array sizes, fault tolerance schemes, test coverage, end-use (datasheet), and test condition specifications of the product are modeled.
Keywords
DRAM chips; fault tolerance; DRAM; array sizes; copula models; customer-oriented figures of merit; dynamic random access memory; fault tolerance schemes; financial modeling; producer-oriented figures of merit; retention times; size 65 nm; variable bit retention time; Arrays; Computational modeling; Correlation; Data models; Gold; Mathematical model; Random access memory; Integrated circuits; dynamic random access memory (DRAM); fault tolerance; reliability; testing; yield models;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2013.129
Filename
6532289
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