Efficient modelling and synthesis procedure of asynchronous sequential logic elements

A model and procedure are developed for synthesising asynchronous sequential logic elements (ASLEs). This model represents the functional behaviour with a more compact form, and the procedure can synthesise them more efficiently than the traditional one. With the delineation of inputs as mode inputs,level inputs and edge inputs from the design specification, a set of equations can be generated which describes the logic module´s functional behaviour. The calculated states from these equations have bipartite adjacency relationships, which can easily be mapped onto an n-cube to obtain race-free state assignments. This procedure can also be applied for the synthesis of an asynchronous sequential logic circuit (ASLC) which has many data inputs and a small number of control inputs