Junctionless Π-gate transistor with indium gallium arsenide channel

The fabrication and characterisation of a gate-first In_0.7Ga_0.3As channel Π-gate junctionless transistor by a CMOS-compatible top-down approach is reported for the first time. The structure uses a simple layer structure and process flow. 3D device simulation shows that the Π-gate structure can deplete the channel carriers more effectively compared with planar and tri-gate devices. The fabricated device with 200 nm gate length shows good transfer characteristics with a Ion/Ioff ratio of ~10⁴ and subthreshold swing of ~210 mV/decade. The results indicate the suitability of the proposed structure for junctionless transistor operation.