• DocumentCode
    1058573
  • Title

    Testing iterative logic arrays for sequential faults with a constant number of patterns

  • Author

    Su, Chih-Yuang ; Wu, Cheng-Wen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    43
  • Issue
    4
  • fYear
    1994
  • fDate
    4/1/1994 12:00:00 AM
  • Firstpage
    495
  • Lastpage
    501
  • Abstract
    Shows that a constant number of test vectors are sufficient for fully testing a k-dimensional ILA for sequential faults if the cell function is bijective. The authors then present an efficient algorithm to obtain such a test sequence. By extending the concept of C-testability and M-testability to sequential faults, the constant-length test sequence can be obtained. A pipelined array multiplier is shown to be C-testable with only 53 test vectors for exhaustively testing the sequential faults
  • Keywords
    combinatorial circuits; logic arrays; logic testing; sequential circuits; C-testability; ILA; M-testability; constant-length test sequence; iterative logic array; iterative logic arrays; logic testing; pipelined array multiplier; sequential fault testing; sequential faults; test pattern generation; test vectors; Circuit faults; Circuit testing; Combinational circuits; Fault detection; Iterative algorithms; Logic arrays; Logic testing; Sequential analysis; Signal processing algorithms; Sufficient conditions;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.278489
  • Filename
    278489