DocumentCode
1059536
Title
A Fast VLSI Multiplier for GF(2m)
Author
Scott, P. Andrew ; Tavares, Stafford E. ; Peppard, Lloyd E.
Author_Institution
Queen´´s Univ., Kingston, Ont., Canada
Volume
4
Issue
1
fYear
1986
fDate
1/1/1986 12:00:00 AM
Firstpage
62
Lastpage
66
Abstract
Multiplication in the finite field 
) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication in ), which is 
in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.
) has particular computational advantages in data encryption systems. This paper presents a new algorithm for performing fast multiplication in ), which is in computation time and implementation area. The bit-slice architecture of a serial-in-serial-out modulo multiplier is described and the circuit details given. The design is highly regular, modular, and well-suited for VLSI implementation. The resulting multiplier will have application in algorithms based on arithmetic in large finite fields of characteristic 2, and which require high throughput.Keywords
Galois fields; Multiplication; VLSI; Very large-scale integration (VLSI); Application software; Arithmetic; Circuits; Computer architecture; Cryptography; Galois fields; Polynomials; Silicon; Throughput; Very large scale integration;
fLanguage
English
Journal_Title
Selected Areas in Communications, IEEE Journal on
Publisher
ieee
ISSN
0733-8716
Type
jour
DOI
10.1109/JSAC.1986.1146305
Filename
1146305
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