DocumentCode
1060351
Title
Guest Editorial System-Level Interconnect Prediction
Author
Dambre, Joni ; Hutton, M.
Volume
15
Issue
8
fYear
2007
Firstpage
853
Lastpage
854
Keywords
Costs; Delay; Electronic design automation and methodology; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Network-on-a-chip; Power system interconnection; Predictive models; Throughput;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2007.900756
Filename
4276777
Link To Document