• DocumentCode
    1061825
  • Title

    An Area Efficient Early {Z} -Test Method for 3-D Graphics Rendering Hardware

  • Author

    Yu, Chang-Hyo ; Kim, Donghyun ; Kim, Lee-Sup

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon
  • Volume
    55
  • Issue
    7
  • fYear
    2008
  • Firstpage
    1929
  • Lastpage
    1938
  • Abstract
    In this paper, we propose a new early z-test which requires a minimized internal memory while removing redundant z and color reads as well as texture reads. The proposed method determines whether a pixel is screened by a certain mask plane which is containing the history of a pixel´s appearance in front of it. If a pixel is screened by the plane, it can be removed. Given an initial position, the method adaptively updates the plane position to maximize the rejected pixels. As a result, on average 39.9% of the memory bandwidth and 21.2% of total power consumption is saved with only a 256 B on-chip memory. The proposed method was implemented into a multimedia system-on-chip with 61 k application-specific integrated circuit (ASIC) gates using a 0.13-mum CMOS process technology.
  • Keywords
    CMOS logic circuits; image texture; power consumption; random-access storage; rendering (computer graphics); system-on-chip; 3-D graphics rendering hardware; CMOS process technology; application-specific integrated circuit gates; memory bandwidth; multimedia system-on-chip; on-chip memory; power consumption; z-test method; 3-D graphics hardware; 3D graphics hardware; ${z}$-test; depth test; early ${z}$-test; early z-test; rasterization engine; rasterization engine (RE); rendering hardware; z-test;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2008.918078
  • Filename
    4447476