DocumentCode
1062649
Title
H-MOS reliability
Author
Rosenberg, Stuart J. ; Crook, Dwight L. ; Euzent, Bruce L.
Author_Institution
Intel Corporation, Santa Clara, CA
Volume
26
Issue
1
fYear
1979
fDate
1/1/1979 12:00:00 AM
Firstpage
48
Lastpage
51
Abstract
H-MOS is a new high-performance n-channel technology with a 1-pJ speed power product. This technology is the result of scaling MOS device dimensions. The effect of thinner oxide integrity and hot electron injection are investigated. A screening technique for thin oxides using high-voltage stressing is presented. Threshold shifts due to hot electron injection were observed to be less than 1 mV. Operating lifetest data predict a failure rate of 0.017 percent/1000 h on 4K static RAM´s built on H-MOS.
Keywords
Contamination; Current density; Electric breakdown; Electron traps; Failure analysis; MOS devices; Maintenance; Secondary generated hot electron injection; Silicon; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1979.19378
Filename
1479956
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