Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems

Transmission of signals on large capacitance paths in a VLSI system may result in substantial degradation of the overall system performance. In this paper minimization of the delay times associated with driving and sensing signals from large capacitance paths by optimizing the fan-out factor of the driver stages, the gain of the input sensing stages, and the path voltage swing are examined. Examples of driving signals on a high capacitance path with two driving schemes are: a push-pull depletion-load driver chain and a fixed driver; and of sensing signals with two sensing schemes: a single-ended depletion-load inverter input stage and a balanced regenerative strobed latch are presented. We conclude that minimum delay time is achieved when the delay times of the successive stages of the driver chain, the high capacitance path, and the input sensing stage are comparable. In general, transmission time of signals in a system is minimized when the delay times of the different stages of the system are comparable.