Finite-difference time-domain method in custom hardware?

Author

Schneider, Ryan N. ; Okoniewski, Michal M. ; Turner, Laurence E.

Author_Institution

Calgary Univ., Alta., Canada

Volume

12

Issue

12

fYear

2002

Firstpage

488

Lastpage

490

Abstract

While the finite-difference time-domain (FDTD) method is very successful in electromagnetics, it is computationally intensive. Reducing the runtime of these simulations, by an order of magnitude or more, would greatly increase the productivity of FDTD users and open new avenues of research. A dedicated hardware implementation that accelerates FDTD computations could provide a means to attain that goal. As the first step, we have implemented a one- and two-dimensional FDTD method in hardware. The experiment proved that computational speed can be increased by as much as two orders of magnitude, and is independent of the number of cells in the simulation.

Keywords

application specific integrated circuits; digital arithmetic; field programmable gate arrays; finite difference time-domain analysis; signal flow graphs; computational speed; custom hardware; dedicated hardware implementation; field programmable gate arrays; fine-grained parallelism; finite-difference time-domain method; one-dimensional method; productivity; two-dimensional method; Acceleration; Arithmetic; Computational modeling; Field programmable gate arrays; Finite difference methods; Flow graphs; Hardware design languages; Parallel processing; Time domain analysis; Voltage;

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2002.805948

Filename

1146695