Charge-coupled device structures for VLSI memories

High-performance CCD´s which can operate at the scaled voltage levels and geometry sizes projected for VLSI memory will require the storage, transfer, and detection of very small charge packets (≤25 000 electrons). The scaling requirements for such CCD structures are shown to be more complex than MOS scaling laws. The device physics of CCD structures which can meet these performance requirements are discussed and related to material and technology problems which must be overcome. For a given area, an enhanced-capacity implant technique is used to increase the storage capacity. A new detection scheme using a bipolar charge amplification allows up to an order of magnitude increase in output sensitivity. Transient subthreshold measurements show that very small interelectrode barriers may exist at low clock voltage overdrive which severely limit CCD transfer efficiency at small geometries.