A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

Author

Savoj, Jafar ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA

Volume

38

Issue

1

fYear

2003

fDate

1/1/2003 12:00:00 AM

Firstpage

13

Lastpage

21

Abstract

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-μm CMOS technology in an area of 1.75×1.55 mm², the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10^-9 with a pseudorandom bit sequence of 2²³-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.

Keywords

CMOS digital integrated circuits; low-power electronics; optical receivers; phase detectors; synchronisation; timing jitter; 0.18 micron; 1.8 V; 10 Gbit/s; 91 mW; CMOS; automatic data retiming; bang-bang phase detector; bit error rate; capture range; clock and data recovery circuit; half-rate binary phase/frequency detector; high-speed optical communication systems; multiphase LC oscillator; peak-to-peak jitter; power dissipation; pseudorandom bit sequence; rms jitter; CMOS technology; Circuit topology; Clocks; Error correction; Jitter; Negative feedback; Phase detection; Phase frequency detector; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.806284

Filename

1158777