Library-Based Cell-Size Selection Using Extended Logical Effort

Given a synthesized digital integrated circuit comprising interconnected library cells, and assuming arbitrary (continuous) sizes for the cells, experimentally, we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). An accurate table-lookup delay model was developed from the precharacterized industrial standard cell library data by making a formal extension to the concept of logical effort that enables optimization of nMOS and pMOS sizes of a cell separately. To the best of our knowledge, this is the first continuous-cell sizing technique exhibiting optimality based upon a table-lookup delay model. We then developed a new delay-bounded dynamic programming-based algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library, which achieves, for the first time, active area versus delay results close to the continuous results. Parallelism was incorporated into the algorithm to enhance efficiency by leveraging multicore processors. After using state-of-the-art commercial synthesis, the application of our cell-size selection tool results in an active area (the sum of all transistor widths) reduction of 36% (on average) for large contemporary industrial designs.