• DocumentCode
    1067658
  • Title

    Epitaxial VVMOS power transistors

  • Author

    Lane, William A. ; Salama, C.A.T.

  • Author_Institution
    University of Toronto, Toronto, Ont., Canada
  • Volume
    27
  • Issue
    2
  • fYear
    1980
  • fDate
    2/1/1980 12:00:00 AM
  • Firstpage
    349
  • Lastpage
    355
  • Abstract
    The design aspects of a V-groove vertical-geometry power MOST (VVMOS) using a simple epitaxial-channel technology, are discussed in this paper. The process has several features including ease of fabrication, good threshold voltage controllability, and high breakdown voltage. Expressions for the on-resistance as a function of device parameters and for the device capacitances as a function of the geometric features of the transistor are derived. Experimental results on fabricated devices are presented.
  • Keywords
    Capacitance; Controllability; Electric variables; Electron devices; Fabrication; Geometry; Helium; Power transistors; Solid state circuits; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1980.19867
  • Filename
    1480660
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1067658