• DocumentCode
    1068591
  • Title

    Open/folded bit-line arrangement for ultra-high-density DRAM´s

  • Author

    Takashima, Daisaburo ; Watanabe, Shigeyoshi ; Nakano, Hiroaki ; Oowaki, Yukihito ; Ohuchi, Kazunori

  • Author_Institution
    Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
  • Volume
    29
  • Issue
    4
  • fYear
    1994
  • fDate
    4/1/1994 12:00:00 AM
  • Firstpage
    539
  • Lastpage
    542
  • Abstract
    An open/folded bit-line (BL) arrangement for scaled DRAM´s is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA´s) for open BL´s and those for folded BL´s are placed alternately between the memory arrays. This arrangement features a small 6F2 memory cell, where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL´s to SA´s, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement
  • Keywords
    DRAM chips; VLSI; code convertors; 64 Mbit; array noise immunity; binary-to-ternary code converter; circuit techniques; coupling noise; dynamic RAM; multiplexer; open/folded bit-line arrangement; scaled DRAM; sense amplifiers; shield effect; ultra-high-density memory chip; Circuit noise; Coupling circuits; Joining processes; Manufacturing; Multiplexing; Noise reduction; Phased arrays; Random access memory; Ultra large scale integration; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.280706
  • Filename
    280706