Real-time implementation of the VSELP on a 16-bit DSP chip

Author

Sunwoo, Myung H. ; Park, Sangil

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

37

Issue

4

fYear

1991

fDate

11/1/1991 12:00:00 AM

Firstpage

772

Lastpage

782

Abstract

A description is given of a real-time implementation of the vector sum-excited linear predictive (VSELP) speech coder, which has been chosen as the digital cellular standard in North America and Japan. This real-time implementation of the VSELP algorithm is realized using a 16-bit general-purpose digital signal processor (GPDSP) with an onchip codec. The principles of the VSELP algorithm and the real-time implementation of the algorithm on the GPDSP chip are addressed. Also discussed are the finite word length effects and possible methods to reduce the effects

Keywords

cellular radio; codecs; digital radio systems; digital signal processing chips; encoding; filtering and prediction theory; speech analysis and processing; standards; 16 bit; Japan; North America; VSELP algorithm; digital cellular standard; finite word length effects; general-purpose digital signal processor; onchip codec; speech coder; vector sum-excited linear predictive; Cellular phones; Channel capacity; Code standards; Communication industry; Digital signal processing chips; Digital signal processors; Signal processing algorithms; Speech coding; Speech processing; Vocoders;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.106939

Filename

106939