Pulse-Stress Dependence of NBTI Degradation and Its Impact on Circuits

In this paper, we provide an overview of the impact of pulsed stress on PMOS devices during negative-bias stress. This paper is divided into the following three sections: 1) DC stress, where the impact of relaxation on the negative bias temperature-instability (NBTI)-induced degradation in FET parameters is discussed, 2) impact of low-frequency (<1 MHz) pulse stress, and 3) high-frequency (>1 MHz) pulse stress, which is studied using ring oscillators (ROs). Finally, the implication of the relaxation during NBTI stress when a PMOS device is subjected to a pulse stress is discussed from the circuit perspective. Based on RO-degradation data measured up to 3 GHz, we conclude that, for circuits operating in a continuous switching mode, NBTI will not be a show stopper.