• DocumentCode
    1072190
  • Title

    P-column gate FET

  • Author

    Asai, Kazuyoshi ; Ishii, Yasunobu ; Kurumada, Katsuhiko

  • Author_Institution
    Nippon Telegraph & Telephone Public Corp., Tokyo, Japan
  • Volume
    1
  • Issue
    5
  • fYear
    1980
  • fDate
    5/1/1980 12:00:00 AM
  • Firstpage
    83
  • Lastpage
    85
  • Abstract
    A new structure for a GaAs JFET (P-Column Gate FET) is proposed, employing p-column shaped gates in an active n-layer on a semi-insulating substrate, where the current flows through spaces between the gate columns. It was found that Be ion implantation can produce p-column gates. The FET I-V characteristics are also presented and discussed.
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1980.25239
  • Filename
    1481101
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1072190