Effects of wafer temperature on plasma charging induced damage to MOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O/sub 2/ plasma exposure increases from 145/spl deg/C to 340/spl deg/C, the damage measured from charge-to-breakdown (Q/sub bd/) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes.