Delay-Line-Based Analog-to-Digital Converters

Author

Li, Guansheng ; Tousi, Yahya M. ; Hassibi, Arjang ; Afshari, Ehsan

Author_Institution

Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY

Volume

56

Issue

6

fYear

2009

fDate

6/1/2009 12:00:00 AM

Firstpage

464

Lastpage

468

Abstract

We will introduce a design of analog-to-digital converters (ADCs) based on digital delay lines. Instead of voltage comparators, they convert the input voltage into a digital code by delay lines and are mainly built on digital blocks. This makes it compatible with process scaling. Two structures are proposed, and tradeoffs in the design are discussed. The effects of jitter and mismatch are also studied. We will present two 4 bit, 1 GS/s prototypes in 0.13 mum and 65 nm CMOS processes, which show a small area (0.015 mm²) and small power consumption (<2.4 mW).

Keywords

CMOS digital integrated circuits; analogue-digital conversion; delay lines; jitter; CMOS process; analog-to-digital converter; digital code; digital delay-line-based ADC design; jitter effect; process scaling; size 0.13 mum; size 65 nm; Analog-digital conversion; CMOS analog integrated circuits; CMOS process; CMOS technology; Delay effects; Delay lines; Flip-flops; Jitter; Signal resolution; Voltage; Analog-to-digital converter (ADC); delay line; scaling;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2009.2020947

Filename

5075832