Estimation of GaAs static RAM performance

A simple and accurate GaAs MESFET model for circuit simulation has been established. Calculated static and dynamic performance have been found to coincide well with experimental results. RAM performance with various FET´s was estimated adopting this model for the simulation. Reduction in series resistance by n⁺doping outside a gate and/or shortening source-drain distance is predicted to be very effective in improving not only access time, but also threshold-voltage margin. A 1-kbit static RAM with 0.8 ns at 400-mW dissipation power will be attainable by using a 0.5-µm gate length FET, with an allowable threshold-voltage standard deviation of 80 mV.