Systematic capacitance matching errors and corrective layout procedures

Author

McNutt, M.J. ; LeMarquis, S. ; Dunkley, J.L.

Author_Institution

Silicon Syst. Inc., Tustin, CA, USA

Volume

29

Issue

5

fYear

1994

fDate

5/1/1994 12:00:00 AM

Firstpage

611

Lastpage

616

Abstract

Precise capacitor ratios are employed in a variety of analog and mixed signal integrated circuits. The use of identical unit capacitors to form larger capacitances can easily produce 1% accuracy, but, in many cases, 0.1% accuracy can provide important performance advantages. Unfortunately, the ultimate matching precision of the ratio is limited by a number of systematic and random error sources. We have analyzed the source and significance of the systematic error sources on actual integrated circuit layouts and isolated five key contributors. Based on this analysis, we have developed a list of generic layout rules and a layout scheme that predict matching accuracies better than 0.1% for the individual systematic error sources using capacitor sizes in the range of 20-40 μm

Keywords

capacitance; circuit layout; errors; integrated circuit technology; linear integrated circuits; mixed analogue-digital integrated circuits; IC layouts; analog integrated circuits; capacitance matching errors; capacitor ratios; corrective layout procedures; error sources; generic layout rules; integrated circuit layouts; mixed signal integrated circuits; Accuracy; Capacitors; Codecs; Dielectric substrates; Error correction; Filters; Integrated circuit interconnections; Integrated circuit layout; Lithography; Parasitic capacitance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.284714

Filename

284714