Modeling Injection of Electrical Fast Transients Into Power and IO Pins of ICs

A SPICE-based model of a microcontroller was developed to investigate its immunity to electrical fast transients (EFTs). The model includes representations of the on-die power delivery network, the ESD protection clamps, and the I/O driver circuits. Several measurement approaches were developed to characterize the linear and nonlinear components within the model. EFTs were injected into pins of the microcontroller to verify the accuracy of the proposed model. General purpose I/O were tested in several configurations (i.e., pull-up-enabled input, logical-high output, and logical-low output). The model was able to predict the voltage waveform and maximum voltage at each pin within 5~6% of the measured values. A parasitic bipolar junction transistor associated with the output driver was found to have a critical impact on the noise coupled to the power bus. The simplicity and accuracy of this model shows its promise for understanding and predicting immunity issues in integrated circuits.