A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

Author

Plouchart, J.-O. ; Ferriss, Mark A. ; Natarajan, Arun S. ; Valdes-Garcia, A. ; Sadhu, B. ; Rylyakov, A. ; Parker, Benjamin D. ; Beakes, Michael ; Babakhani, A. ; Yaldiz, Soner ; Pileggi, Larry ; Harjani, Ramesh ; Reynolds, S. ; Tierno, Jose A. ; Friedman,

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

60

Issue

8

fYear

2013

fDate

Aug. 2013

Firstpage

2009

Lastpage

2017

Abstract

A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.

Keywords

CMOS integrated circuits; circuit noise; circuit tuning; elemental semiconductors; jitter; mean square error methods; millimetre wave integrated circuits; phase locked loops; silicon; silicon-on-insulator; voltage-controlled oscillators; PLL power consumption; RMS; SOI-CMOS PLL; Si; adaptive biasing scheme; adaptively biased VCO; frequency 23.5 GHz; frequency tuning; jitter; millimeter wave integrated circuit; power 27.2 mW; size 32 nm; Millimeter wave integrated circuits; phase locked loops; phase noise; silicon-on-insulator;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2013.2265961

Filename

6541965