A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

Author

Dong Uk Lee ; Kyung Whan Kim ; Kwan Weon Kim ; Kang Seol Lee ; Sang Jin Byeon ; Jae Hwan Kim ; Jin Hee Cho ; Jaejin Lee ; Jun Hyun Chun

Author_Institution

R2 Center, SK hynix, Icheon, South Korea

Volume

50

Issue

1

fYear

2015

fDate

Jan. 2015

Firstpage

191

Lastpage

203

Abstract

Motivated by a graphics memory system that achieves multiplied bandwidth by the number of memories per system, HBM DRAM adopts a brand new architecture, with many technical changes and challenges. The first main change in the architecture is the stacked memory structure with TSV array, which has independent bandwidth per slice. The second is semi-independent row, column command interface, which enhances effective performance. For supporting high bandwidth, this chip has fine pitch microbump interface. Methods for testing microbump are explained. 8 Gb stacked HBM is fabricated with chip-on-wafer process and tested with high-frequency wafer probing. Using chip-on-wafer test results, 128 GB/s at 1.2 V supply voltage is achieved.

Keywords

DRAM chips; built-in self test; three-dimensional integrated circuits; wafer level packaging; HBM DRAM; TSV array; bit rate 128 Gbit/s; chip-on-wafer process; fine pitch microbump interface; graphics memory system; high-frequency wafer probing; microbump testing; semi-independent row column command interface; stacked memory structure; storage capacity 8 Gbit; voltage 1.2 V; Bandwidth; Clocks; Computer architecture; Latches; Random access memory; Testing; Through-silicon vias; Built-in-self-test; DRAM; PHY; TSV; calibration; chip-on-wafer; known good stack; loopback; microbump; stacked-memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2360379

Filename

6923498