An optoelectronic CMOS circuit implementing a simulated annealing algorithm

Author

Dupret, A. ; Belhaire, Eric ; Rodier, Jean-Claude ; Lalanne, Philippe ; Prevost, Donald ; Garda, Patrick ; Chavel, Pierre ; Dupret, A.

Author_Institution

CNRS, Univ. de Paris-Sud, Orsay, France

Volume

31

Issue

7

fYear

1996

fDate

7/1/1996 12:00:00 AM

Firstpage

1046

Lastpage

1050

Abstract

An original optoelectronic implementation of simulated annealing is presented. A compact and simple optical system provides a chip with arrays of independent random noise sources. The silicon chip is composed of a mesh of computing cells. Each cell includes both analog and digital circuits and includes two photosensors. A detailed analysis of this cell is given including a presentation of the design constraints. A 4×4-cells prototype chip was implemented in a 1 μm CMOS digital technology and was successfully operated at 20000 iterations per second. The measurements and characterization of this chip made possible the successful design of a 600-cells chip also presented. These results demonstrate the video-rate application of simulated annealing to early vision tasks

Keywords

CMOS integrated circuits; computer vision; integrated optoelectronics; simulated annealing; 1 micron; CMOS digital technology; Si; analog circuits; computing cells; design; digital circuits; early vision; optoelectronic CMOS circuit; photosensors; random noise; simulated annealing algorithm; stochastic silicon retina; video rate; CMOS technology; Circuit noise; Circuit simulation; Computational modeling; Digital circuits; Optical arrays; Optical noise; Prototypes; Silicon; Simulated annealing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508220

Filename

508220