A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication

Author

Yoshimura, Tsitmu ; Kondoh, Harufusa ; Matsuda, Yoshio ; Sumi, Tadashi

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Itami, Japan

Volume

31

Issue

7

fYear

1996

fDate

7/1/1996 12:00:00 AM

Firstpage

1063

Lastpage

1066

Abstract

A compact 622-Mb/s/port bit/frame synchronizer is presented. Sampling equally-phased clocks from a phase-locked loop (PLL) at the data transition edges, the bit synchronizer selects the optimum one as the extracted clock. An elastic serial-to-parallel converter is used for the frame synchronization. The circuit is designed for a 32-port ATM switch chip, achieving 622-Mb/s port capacity by four parallel 156-Mb/s bits. Using 0.5-μm CMOS technology, the circuit was verified by simulations. The bit synchronizer consumes only 15 mW under typical conditions

Keywords

CMOS digital integrated circuits; asynchronous transfer mode; circuit analysis computing; clocks; digital phase locked loops; synchronisation; 0.5 micron; 15 mW; 622 Mbit/s; ATM switch chip; CMOS technology; bit/frame synchronizer; circuit simulation; data transition edges; elastic serial-to-parallel converter; equally-phased clocks; high-speed backplane data communication; phase-locked loop; port capacity; Asynchronous transfer mode; Backplanes; CMOS technology; Circuits; Clocks; Data mining; Phase locked loops; Sampling methods; Switches; Synchronization;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508223

Filename

508223