Creator: new advanced concepts in concurrent simulation

Creator is a concurrent simulator for design verification and fault simulation of large circuits that highly integrates several traditional and innovative techniques. This is achieved by the introduction of a minimal information concept. Traditional techniques derived from previous works are Multiple List Traversal (MLT), trigger inhibition, fraternal event processing, list events, acid clock suppression, whereas the new ideas are function lists and evaluation functions, persistence time, positioning algorithm, evaluation triggering algorithm, combination of Single List Traversal (SLT) and MLT, and the implementation of transport delay in fault simulation. Generally the concurrent algorithm increases in complexity and the implementations grow in size and lose in performance as soon as higher abstraction levels are added beyond the gate one. To overcome this limitation, all the Creator´s techniques are not related to a specific abstraction level and lead to an intrinsic multilevel concurrent fault simulator. Experimental results are reported to compare Creator with our previous simulator and the state-of-the-art commercial simulator Verifault-XL on several platforms