A sense and restore technique for multilevel DRAM

A technique for storing and retrieving 2 b of data encoded as 4 voltage levels in a single DRAM memory cell is described. The 4 data levels and sense amplifier reference levels are created through simple charge redistribution techniques on local bitlines. Memory cells, sense amplifiers, and wordline drivers identical to standard DRAM are employed. A SPICE simulation using a representative 16 M DRAM process model shows correct sense and restore operation, with accurate generation of reference levels. The capacity of DRAM chips can be doubled with the addition of multilevel support circuitry that occupies less than 20% of die area