Package thermal resistance model: dependency on equipment design

A physical model is used to explain how package thermal resistance can increase by a factor of four even though cooling conditions remain constant. The model accounts for the discrepancy between observed system thermal performance of a package and data sheet thermal resistance values which are not accompanied by qualifying data consisting of chip thermal resistance, board temperature rise over ambient, convection coefficient, mounting sensitivity, and power dissipation. In all, eight constants are needed to predict inherent increases in package thermal resistance when going from a lab condition to an equipment condition. These constants and procedures for obtaining them are given for dual in line (DIP), pin grid array (PGA), small outline transistor (SOT), and plastic leaded chip carrier (PLCC) packages. A foundation is established for routinely including the constants in component data sheets and for strengthening thermal measurement standards