SH3: high code density, low power

Author

Hasegawa, Atsushi ; Kawasaki, Lkuya ; Yamada, Kouji ; Yoshioka, Shinichi ; Kawasaki, Shumpei ; Biswas, Prasenjit

Author_Institution

Dept. of Microcomput. Syst. Eng., Hitachi Ltd., Tokyo, Japan

Volume

15

Issue

6

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

11

Lastpage

19

Abstract

Hitachi´s SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding improvement in instruction-fetch latency lead to higher performance than typical 32-bit RISC architectures achieve. These features, small die size, and low power consumption make SH3 an ideal microprocessor for portable computing systems or multimedia systems

Keywords

computer architecture; microprocessor chips; reduced instruction set computing; 32-bit RISC architecture; MMU; SH3; high code density; instruction-fetch latency; low power; low power consumption; microprocessors; on-chip cache; small die size; software-programmable power management; Control system synthesis; Counting circuits; Energy consumption; Energy management; Microprocessors; Multimedia systems; Power system management; Reduced instruction set computing;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.476254

Filename

476254