DocumentCode
1087206
Title
Verification of models for fabrication of Arsenic source-drains in VLSI MOSFET´s
Author
Albers, John ; Roitman, P. ; Wilson, Charles L.
Author_Institution
National Bureau of Standards, Washington, DC
Volume
30
Issue
11
fYear
1983
fDate
11/1/1983 12:00:00 AM
Firstpage
1453
Lastpage
1462
Abstract
The understanding of the effects of both low- and high-temperature anneals of arsenic implanted into silicon is critical in the calculation of p-n junction profiles of sources and drains in short-channel MOSFET´s. The work reported here uses a sample matrix of arsenic implanted into silicon over a wide range of fluences and annealed in both the low- and high-temperature regimes. This matrix of samples was measured by means of Rutherford Backscattering Spectrometry (RBS), spreading resistance (Rsp), and Secondary Ion Mass Spectrometry (SIMS). The measurement techniques are compared with each other, with the predictions of ion-implantation models, and with the annealing/diffusion models. Comparison of the RBS data from more than one experiment indicates that high-quality quantitative analysis requires more complex calibration data for the detector than is usually available. The Rsp data obtained on the low-temperature annealed samples did not yield reasonable arsenic profiles, both with respect to the peak location and profile shape. The measurement technique which was most consistent with theoretical models and most reproducible from one experimenter to another is the SIMS technique. Calculations of the annealed profiles were found to be in agreement with the SIMS data, at temperatures greater than 900°C, when the form used by Fair was employed. A large adjustment in the parameters of the charge vacancy reaction is necessary; a much smaller adjustment is required in the parameters of the extrinsic diffusion reaction. The accuracy obtained here is typical of much available data and is sufficiently accurate for 2-µm MOS device characterization, but not sufficient for submicrometer devices.
Keywords
Annealing; Backscatter; Electrical resistance measurement; Fabrication; Mass spectroscopy; Measurement techniques; P-n junctions; Predictive models; Silicon; Very large scale integration;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1983.21323
Filename
1483224
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