DocumentCode
1089421
Title
An experimental nanosecond Josephson 1K RAM using 5-µm Pb-alloy technology
Author
Yamamoto, M. ; Yamauchi, Y. ; Miyahara, K. ; Kuroda, K. ; Yanagawa, F. ; Ishida, A.
Author_Institution
Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, Japan
Volume
4
Issue
5
fYear
1983
fDate
5/1/1983 12:00:00 AM
Firstpage
150
Lastpage
152
Abstract
A high-speed fully decoded Josephson 1K RAM has been designed and tested. Several bits of the 1K RAM were successfully operated with a typical read access time of 3.3 ns and associated power dissipation of 2.0 mW. The chip, containing about 10 000 Josephson junctions, was fabricated using 5-µm Pb-alloy technology, including a novel junction oxide barrier formation technique. A nondestructive readout (NDRO) Josephson ring cell operating with all current levels equal and an on-chip timing circuit for read/write operations were employed.
Keywords
Decoding; Equivalent circuits; Interferometers; Latches; Oxidation; Pulse generation; Read-write memory; Switching circuits; Timing; Writing;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1983.25683
Filename
1483427
Link To Document