Cell height driven transistor sizing in a cell based static CMOS module design

We considered a post-layout transistor sizing problem in a static CMOS module layout. The transistor sizer proposed in this paper is different from previous approaches which work on a full-custom layout and optimizes a module layout on several rows of automatically generated leaf cells. The sizing is performed at two levels. At the module level, a leaf cell is chosen based on a height slack (usable area) and timing slack. At the cell level, the cell is sized based on a width constraint imposed from the module level. The object is to minimize the difference of the actual arrival time and the required arrival time. The problem of sizing a cell is formulated as a nonlinear program. A new objective function is defined so that not only the long delay is shortened but also the short delay is lengthened. We applied an extended empirical method to solve the nonlinear programming problem. A benchmarking process has been conducted at both cell level and module level. Experiments on a set of cells show that an average of 26% performance improvement was obtained by using 0.06% more area. Moreover, for a leaf cell with multiple outputs, the sizer can indeed simultaneously make the long delay paths shorter and short delay paths longer. The results of a module level experiment show that by using height slack, the maximum delay of the circuit can be reduced up to 17.7% without area penalty for the example shown