Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability

Author

Kuroda, Tadahiro ; Fujita, Tetsuya ; Noda, Makato ; Itabashi, Ya Sushi ; Kabumoto, Satohiko ; Wong, T.S. ; Beeson, Dave ; Gray, Dave

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

31

Issue

6

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

819

Lastpage

827

Abstract

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied

Keywords

VLSI; bipolar logic circuits; emitter-coupled logic; logic gates; 0.25 mW; 0.55 pF; 1.2 micron; 300 ps; double-poly self aligned bipolar technology; gate speed; level-sensitive active pull-down ECL; load-dependent capacitive coupling; output level; power consumption; process complexity; regulated reference voltage; self-adjusting driving capability; Capacitors; Circuit simulation; Delay; Energy consumption; Resistors; Steady-state; Switching circuits; Tail; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.509868

Filename

509868