Design for testability of sequential circuits

The paper presents a new approach for design-for-testability (DFT) of sequential circuits. The proposed approach is based on augmenting the system under test (SUT) which is modelled as a Mealy machine, with circuitry such that the combinational part of the SUT and the sequential part (i.e. The flip-flops can be tested independently (disjoint testing). A partial parallel scan method is used with a multiphase technique. Two extra input lines are required with no modification to the memory elements. It is proved that the proposed approach provides 100% fault coverage for a single nonredundant fault and requires a significant smaller number of phases than previous scan approaches. Simulation results shows that, for benchmark circuits, the proposed approach requires a significant lower number of tests than previous approaches. The area overhead for either a PLA or a two-level realisation of the combinational part of the SUT is very modest