Single-chip design of bit-error-correcting stack decoders

The design of a single-chip VLSI system to implement the Zigangirov-Jelinek sequential decoding algorithm for bit-error-correction is described and the dependence of performance on design parameters is discussed. By virtue of being self-contained, having few input and output pins, and processing stack elements once each clock cycle, the system should be capable of high-speed decoding. For constraint length 21, rate 1/2 codes, and 3-b soft decision detection, it is found that a system containing approximately 25000 stack cells reduces errors in a 3-dB signal-to-noise level environment, corresponding to 7.8% hard decision error rate, by two orders of magnitude. Higher decoding gain is obtained at lower noise levels through the use of a relatively long constraint length. The constraint length is not limited by the architecture. Chip area estimates needed to obtain prescribed decoded error rates and average decoding rates are also described and indicate that an effective system is potentially achievable with current technology