Latchup criteria in insulated gate p-n-p-n structures

Latchup in insulated-gate p-n-p-n structures may be due either to the well-known thyristor action or to a regenerative feedback originating from substrate bias in the MOS gate. Simple models are presented to interpret and to predict both latching modes. It is shown that these two latching modes may occur consecutively as the current level rises, and that the device may, therefore, exhibit three distinct regions of forward operation. Experiments on special test devices in which the p-base region can be accessed externally support the theory well.