• DocumentCode
    1100895
  • Title

    Computer Reduction of Two-Level, Multiple-Output Switching Circuits

  • Author

    Su, Yueh-hsung ; Dietmeyer, Donald L.

  • Author_Institution
    IEEE
  • Issue
    1
  • fYear
    1969
  • Firstpage
    58
  • Lastpage
    63
  • Abstract
    An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures.
  • Keywords
    Algorithm, combinational logic synthesis, logic design automation, multiple-output switching functions, reduction of two-level logic.; Circuit synthesis; Combinational circuits; Costs; Design automation; Diodes; Input variables; Logic design; Minimization methods; Network synthesis; Switching circuits; Algorithm, combinational logic synthesis, logic design automation, multiple-output switching functions, reduction of two-level logic.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1969.222525
  • Filename
    1671118
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1100895