Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 μm CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.