Delay-Free Asynchronous Circuits with Constrained Line Delays

Armstrong, Friedman, and Menon have shown how fundamental-mode normal flow tables can be realized without delay elements under the constraint that line delays do not exceed a given chain of gate delays. The state assignments for these tables are designed to yield noncritical races and minimum transition times. This note presents an independently discovered alternative to their design procedure and also extends their results to totally sequential (or race-free) state assignments. The almost totally sequential state assignment is defined and presented as an approach toward delay-free realizations, under suitable line delay constraints, of nonnormal flow tables.