DocumentCode
1102500
Title
Monolithic integration of a planar embedded InGaAs p-i-n detector with InP depletion-mode FET´s
Author
Tell, Benjamin ; Liao, Andrew S.H. ; Goebeler, Kevin F Brown ; Bridges, Thomas J. ; Burkhardt, Gardner ; Chang, T.Y. ; Bergano, Neal S.
Author_Institution
AT&T Bell Laboratories, Homedell, NJ
Volume
32
Issue
11
fYear
1985
fDate
11/1/1985 12:00:00 AM
Firstpage
2319
Lastpage
2321
Abstract
We report the operation of a fully integrated p-i-n FET circuit based on a planar embedded In0.53 Ga0.47 As p-i-n detector and load resistor with InP depletion-mode FET´s. The structure employs selective growth of InGaAs on a semi-insulating InP substrate and selective ion implantation of Si and Be into the InP and InGaAs, respectively. For a 10-9bit error rate at 1.54 m, the circuit achieves a sensitivity of -34 dBm at 90 Mbit/s and -29.5 dBm at 295 Mbit/s.
Keywords
Annealing; Bridge circuits; Detectors; Etching; FET circuits; Implants; Indium gallium arsenide; Indium phosphide; Monolithic integrated circuits; PIN photodiodes;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1985.22277
Filename
1485023
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