DocumentCode
1103133
Title
A High-Speed Carry Circuit for Binary Adders
Author
Weller, Charles W.
Issue
8
fYear
1969
Firstpage
728
Lastpage
732
Abstract
A high-speed carry circuit for binary parallel adders is described. The circuit consists of emitter followers connected in series to form a transmission path for carry signals obtained from the individual bits of the adder.
Keywords
Binary parallel adders, computer simulation, logic circuitry, operational results, simple fast carry.; Adders; Circuit analysis computing; Circuit optimization; Circuit simulation; Computational modeling; Computer simulation; Logic circuits; Propagation delay; Schottky barriers; Schottky diodes; Binary parallel adders, computer simulation, logic circuitry, operational results, simple fast carry.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1969.222755
Filename
1671348
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