Spacer Engineering-Based High-Performance Reconfigurable FET With Low OFF Current Characteristics

In this letter, we optimize and investigate for the first time the effect of source/drain spacer oxide on the performance of a dual gate ambipolar silicon nanowire field effect transistor. Using extensive 3-D TCAD simulations, we show that the OFF-state leakage can be reduced by more than two orders of magnitude owing to the combined use of HfO₂ spacer and high-κ gate dielectric, resulting in an enhanced ON/OFF current ratio >10¹¹ for both n and p-FET as compared with reported values of ~10⁹. Comparing with the existing experimental dual and trigate ambipolar devices, 64.1% improvement in subthreshold slope for n-FET and 61.8% (40.9%) for n (p-FET) are observed. Having, an improvement in the ON-state current with J_Dmax of 767.51 (263.05) kA/cm^-2 for n-FET (pFET), the device promises excellent ultra low power logic performance, with ambipolarity.